1. Field of the Invention
The present invention relates to an array of cells including a selection bipolar transistor and a fabrication method thereof. In particular, the invention refers to a cell array of a phase change memory (PCM) device, without being limited thereto.
2. Description of the Related Art
As is known, phase change memory cells utilize a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct resistivity. Specific materials that may be suitably used in phase change memory cells are alloys of elements of the VI group of the periodic table as Te or Se, also called chalcogenides or chalcogenic materials. Thus a thin film of chalcogenic material may be employed as a programmable resistor, switching between a high and a low resistance condition.
The use of chalcogenic storage elements has been already proposed to form a memory cell. To avoid disturbances caused by adjacent memory cells, the chalcogenic element is generally coupled with a selection element, generally a MOS transistor or a diode.
A possible organization of a PCM array is shown in FIG. 1. The memory array 1 of FIG. 1 comprises a plurality of memory cells 2, each including a storage element 3 of the phase change type and a selection element 4 formed as a bipolar PNP transistor. The same architecture may be however used for any array of storage elements that are selectively addressed through respective bipolar transistor selection elements.
The memory cells 2 are arranged on rows and columns. In each memory cell 2, the storage element 3 has a first terminal connected to an own bit line BLn−1, BLn, BLn+1, . . . , and a second terminal connected to an emitter of an own bipolar transistor 4; the bipolar transistor 4 has a base connected to an own control line, also called word line WLn−1, WLn, WLn+1, . . . and a grounded collector.
In order to address the storage element 3 belonging to a specific cell 2, for example the one connected to bit line BLn and to world line WLn, the bit line connected to the addressed cell (selected bit line BLn) is biased at a high voltage VOP and all the other (unselected) bit lines BLn−1, BLn+1, . . . are grounded. Furthermore, the word line connected to the addressed cell (selected word line WLn) is grounded and all the other (unselected) word lines WLn−1, WLn+1, . . . are biased at VCC, so that the bipolar transistors 4 not connected to the selected word line are held off.
CMOS compatible processes for manufacturing PCM have been already proposed. For example, U.S. patent application Ser. No. 10/313,991, filed on Dec. 5, 2002 and entitled Small Area Contact Region, High Efficiency Phase Change Memory Cell and Fabrication Method Thereof, which is incorporated by reference herein in its entirety, describes a process providing a small area contact between the chalcogenic region and the resistive electrode. In this prior patent application, each cell is housed in an own active area. This prior application however does not deal with the optimization of the layout of the memory cell.
Since electronic devices are required to be more and more compact, it is desired to provide a highly compact layout for the array structure of FIG. 1.